Output devices (e.g. buffer/drivers) for digital (CMOS) signal processing systems and components, such as high density CMOS arrays, must be sufficiently large to handle the substantial current requirements (including large current spikes) of attendant signal transmission circuits, which often include a high capacitance bus. Despite their increased size, however, these devices are still relatively slow in switching the bus from one logic level to another. One proposal to reduce logic level switching time is to predrive the bus by means of a circuit which switchably couples a pair of logic level reference potentials to a bus drive node and, in response to the onset of a voltage level transition, controllably gates a pair of switching devices, so as to drive the node, and thereby the bus, to a voltage level that is intermediate the destination logic level. Predriving the bus to this intermediate level immediately prior to an actual logic transition can substantially reduce the switching time from that required to complete a full logic level swing to a shorter period of time required to transit from the intermediate level to the destination voltage. Predriving significantly reduces ground spiking, which is a major system problem when many outputs are switching simultaneously. However, in the course of a predrive operation, it is often the case that both switching devices are rendered conductive simultaneously, thereby sinking current to ground. Consequently, although a dual switching device predrive circuit is capable of predriving the bus and thus able to substantially reduce output current spikes, it often consumes power unnecessarily.